1. Field of the Invention
This invention relates in general to a capacitor structure and, in particular, to a capacitor structure for use in dynamic random access memory integrated circuit devices and a method of fabricating the capacitor.
2. Technical Background
Dynamic random access memory (DRAM) has been a widely utilized in computer systems and is typically embodied in an integrated circuit (IC) device. Memory cells used in high capacity DRAM IC devices comprise a metal-oxide semiconductor field-effect transistors (MOSFETs), each having its gate terminal connected to a word line of the IC device. The source and drain regions of each MOSFET are connected, respectively, to a bit line of the memory IC device and to ground potential through a capacitor.
As is well known to persons skilled in this art, a capacitor is utilized for the storage of the memory content of each memory cell. The bit in question, either a one or a zero, as stored in the memory cell, is determined by whether or not the capacitor is charged or discharged. Due to the inherent nature of the DRAM design, the capacitor should possess high capacitance in order to maintain its memory content for as long a period of time as possible.
Since MOSFETs are bi-directional switches, the source and drain regions of a MOSFET in a DRAM memory cell reverse themselves during the read and write cycles, therefore, the source and drain regions are represented as source/drain regions in the description of this invention.
Conventional DRAM devices had a drawback of having a capacitor structure for each memory cell with relatively small capacitance for storing the memory contents of the cell. Basically, the capacitors are fabricated by forming field oxide layer, gate oxide layer, a first polysilicon layer, and a gate spacer oxide layer sequentially on a silicon substrate. A silicon oxide layer is then formed, a contact opening is etched at the designated source/drain region, and a second layer of polysilicon layer covers the contact opening. After this, a dielectric layer, such as NO (nitride/oxide), or ONO (oxide/nitride/oxide), is formed on the exposed surface of the second layer of polysilicon layer, and then a third layer of polysilicon layer is formed to complete the capacitor structure. Within this structure, the second polysilicon layer, the dielectric layer, and the third polysilicon layer constitute the capacitor for the memory cell. This prior art capacitor, which is referred to as a stacked capacitor structure, is described subsequently in greater detail with reference to FIGS. 1 and 2.
As is well known in this art, the capacitance of the capacitor is directly proportional to the surface area of the dielectric layer formed between the second and third polysilicon layers. The larger the surface area, the larger the capacitance. With the constant trend to make ICs which are smaller and smaller, component density is becoming greater and all components in IC devices are becoming smaller. This is true for the foregoing stacked capacitors, but making the capacitors smaller reduces their capacitance and also reduces the time during which they will store data. Additionally, a complex fabricating process is used to make such stacked capacitors, which process expensive to utilize.
To solve the problems outlined above for the conventional stacked capacitor structure, a trenched capacitor configuration was proposed which achieved higher capacitance. With the trenched capacitor configuration, two constructions are possible. On a P-type silicon substrate, a field oxide layer, a gate oxide layer, a first polysilicon layer, and N.sup.+ -type source/drain regions are formed to constitute a transistor. An anisotropic etching process, such as reactive ion etching (RIE), forms a trench in the P-type silicon substrate. A dielectric layer and a second polysilicon layer are subsequently formed in the trench to constitute the capacitor. Finally an oxide layer is formed on top, and metal is plated in the contact opening to complete a memory cell unit for a DRAM memory device. Moreover, to obtain better capacitor quality, an isolation layer, a second polysilicon layer, a dielectric layer, and a third polysilicon layer are sequentially formed after the trenched capacitor is constructed.
Such trenched capacitors enjoy higher capacitance; however, due to the small size of components required in contemporary IC devices, the aspect ratio of the trench is increasing, and as it increases, it slows down the fabricating process noticeably. Moreover, the vertical trench construction induces stress in the entire silicon device, resulting inevitable crystalline defects, thereby reducing the quality of the device.